Appendix B: Verilog2VHDL Translation Reference

Verilog2VHDL translates Verilog to VHDL using a combination of IEEE and tool-specific packages. The tool provides support for comprehensive modeling styles and maintains hierarchy during the translation. In this chapter, various supported constructs are discussed.

The rest of the chapter is organized as follows: For every construct supported by Verilog2VHDL, the general Verilog and VHDL semantics are given, followed by an example illustrating the construct in both languages. Special notes are given when required. The user is advised to refer to the VHDL LRM and Verilog LRM for detailed explanations.

Objects and Types

Verilog has the following types defined:

Integer, real and time variables

In VHDL, three classes of objects (as outlined below) are defined, each of which can be a scalar, composite, access or file type:

Verilog2VHDL translates registers, integer, real and wire variables (henceforth referred to as Verilog objects) declared in Verilog to VHDL objects of a specific class based on the following criteria :

1. If a Verilog object is declared inside a task or function, the corresponding VHDL object class is VARIABLE.

2. If a Verilog object is declared as a parameter, the VHDL object class is CONSTANT.

3. All others Verilog object declarations get the VHDL object class SIGNAL .

Verilog and VHDL are based on the same 4-level logic system (0,1 ,X,Z). Verilog2VHDL uses the IEEE standard 9-level std_ulogic type to translate the logic-levels. The logic levels in Verilog translate to the VHDL std_logic_1 164 package 9-level system in the following way:

Logic Level Mapping

The basic Verilog data type wire is equivalent to the VHDL resolved type std_logic. Similarly, a vector in Verilog is equivalent to the VHDL resolved type std_logic_vector.

The primary design unit in Verilog is the module . The equivalent representation in VHDL is an entity and architecture declaration. The standard Verilog and VHDL syntax for design unit declaration and an example illustrating the concept are shown below:

Parameter Declaration

Constants can be declared in Verilog using the parameter declaration. The corresponding VHDL declaration is a generic in the entity declaration.

Register and Net Declaration

There are two main types of data types in Verilog: Registers and Nets. Registers are a data type to model data storage. They can hold their value until the next assignment. Nets, on the contrary, do not store any value (except trireg), and instead take the value of the driving gate or assignment. They are primarily used to represent connections between structural entities. VHDL models both registers and nets using the type signal . Signals in VHDL are used both for electrical connections and storing values.

Special Note: Register declarations and other Verilog declarations inside user defined tasks and functions are modeled as VHDL variables .

Memory Declaration

Verilog HDL models memories as arrays of register variables. They are typically used to model Read only memories (ROM) or Random access memories (RAM). Translation of memory types to VHDL is straight forward. A special type is created for this purpose in output VHDL.

Integer Declaration

One of the types allowed in Verilog is the Integer type. Integer types in Verilog are translated to a resolved subtype of the pre-defined integer type in VHDL.

Special Note : The resolved subtype v2v_integer , and type integer_array are declared in the v2v_types package available in the types.vhd file.

Real Declaration

Types allowed in Verilog include the real type. Real types in Verilog are translated to the pre-defined real type in VHDL.

Module Instantiation

Both Verilog and VHDL are hierarchical description languages, and allow modules to be embedded inside other modules. This process is also known as module instantiation. Higher level modules instantiate modules, and communicate with them through the ports on the instantiated module. The functionality of module instantiation is equivalent in both languages.

Gate Instantiation

Verilog is a rich language for modeling at low levels of abstraction. It has built-in primitives like n-input nand gates and buffers. VHDL, on the other hand, is more suited for modeling at higher levels. Though it is possible to create entities corresponding to Verilog gates, Verilog2VHDL translates a gate instantiation for almost all gates into equivalent VHDL concurrent signal assignments.

Always Statement

Special Note: `negedge' is a library function provided in the timing package (file timing.vhd ).

Initial Statement

The initial statement is similar to the always statement, except that it executes only once during the entire simulation run. It is functionally equivalent to a VHDL process with an infinite wait statement at the end of the sequential body.

Register initialization in initial statements without event control are handled as a special case. If the register initialization is the first statement in the initial block without event control (precedes ALL wait statements), the statement is mapped to a signal initialization statement in VHDL. The following example shows this special case for register `a'.

Conditional if-else-if Statement

Both languages support the conditional `if statement' and the translation is mostly straightforward, with a few exceptions. In Verilog, the result of an `if expression' can be (0,1,X,Z). In VHDL, the `if expression' has to decode to the boolean type in VHDL (FALSE, TRUE). All Verilog expressions do not map directly to VHDL. A typical example is the following `if expression' (this type of expression will be referred to a `non­boolean' expression in ensuing discussion) :

if (a)

There is no direct equivalent in VHDL, because the above `if expression' tests if `a' is `1', in the case `a' is a register data type, or if `a' has a value other than `0', if `a' is an integer type. To preserve logical equality during translation, Verilog2VHDL translates a non­boolean `if expression' in Verilog to a boolean expression. A negation test is applied to the scalar or vector instead, to preserve the logic. An example illustrates the translation below. In the example, the first `if expression' is not a boolean expression by itself. Hence, Verilog2VHDL maps the `if expression' in Verilog to VHDL by first applying the std_logic_1 164 package translation function `To_Bit' to the register variable and then testing for a non-zero value. The translation function `To_Bit' is required to discard cases involving unknowns.

Special Note : The library function `To_bit' is available in the Std_logic_1164 package.

Conditional 'case' Statement

The case statement uses the same reasoning in both languages; both are multi-way decision statements which test for a matching expression and branch accordingly. There are, however, some limitations in VHDL, which does not have direct equivalent statements for `casex' and `casez'. The translation of ` casex' and `casez' statements is detailed in the next section.

Conditional 'casex' and 'casez ' Statement

`casex' and `casez' statements are special purpose case routines provided in the Verilog language for `dontcare' comparison. VHDL has no direct equivalent, but Verilog2VHDL writes out the equivalent VHDL for a `casex' or `casez' statement. Each of these statements is translated to an equivalent VHDL `if' statement and the sequential statements are updated accordingly.

Special Note : `casex' and `casez' are library functions available in the utils package (file utils.vhd).

Looping Statements

Looping, or iteration schemes found in Verilog can be easily translated to VHDL. Verilog2VHDL supports `for', `repeat', `while' and `forever' statements.

Special Note: The Verilog `for' statement is equivalent to the VHDL `for' statement only when the Verilog `for' has static bounds, and the loop variable (`i' in the example above) is incremented by one (i = i + 1) or decremented by one (i = i - 1). The loop variable `i' is not available as a signal in VHDL, and hence cannot be accessed when used as the target for assignments, other than incrementing (decrementing) by one. For this reason, the Verilog `for' is mapped to the VHDL `WHILE' loop. In doing so, we also gain access to the loop variable `i'.

Continuous Assignments

A continuous assignment in Verilog is a statement that executes every time the right hand side of the an assignment changes. This is wholly equivalent to the concurrent signal assignment in VHDL with inertial delays.

Procedural Assignments

Procedural assignments are used to assign values to register, integers, real or time variables. These types of assignments are normally present in always/initial statements, tasks and functions. Procedural assignments can have delay, event or repeat control. All cases are translated correctly to functionally equivalent VHDL.The subtle differences when translating a Verilog procedural assignment to a VHDL assignment are shown below.

Special Note: Explanation follows about the `wait for 0 ns' statements in the VHDL code corresponding to a Verilog blocking assignment without timing control. In Verilog, events due to blocking assignments always occur. Statements following the blocking assignments occur only after the blocking assignment has taken effect. In VHDL, however, simulation time advances only after a wait statement, and assignments take effect when simulation time advances. For this reason, it is necessary to insert a `wait for 0 ns' after a sequential signal assignment in VHDL for cases where no delay in specified.

Non-blocking Procedural Assignment

The non-blocking Verilog procedural is a way to model transport delays in signal assignments; i.e it does not matter what order you make the assignments in a procedural dataflow. VHDL assignments are inherently non-blocking, and hence it is easy to translate Verilog non-blocking assignments.

Special Note: `posedge' function is available in the timing package.

Compiler Directives

Verilog supports numerous compiler directives. In this version of Verilog2VHDL, only the `timescale and `define compiler directives are supported. `define compiler directives are translated as system - wide generic declarations i.e. all modules following the `define statement have a generic interface list corresponding to the `define statement. The time unit specified with the `timescale directive is used as the time unit for VHDL.

User-Defined Tasks and Functions

User-defined tasks and functions are used extensively in behavioral Verilog. They encapsulate blocks of sequential statements and are invoked from within the module. Additionally, arguments can be passed and exchanged through these calls. Though VHDL has equivalent procedures known as `Subprograms', they differ from Verilog tasks and functions in the following ways:

1. To execute a signal assignment in a VHDL subprogram, it is necessary for the signal to be available in the list of interface elements of the subprogram. This is not a requirement in Verilog. Hence, Verilog2VHDL adds signals that are driven from within a Verilog task or function as interface elements to the corresponding VHDL subprogram.

2. In VHDL, it is not possible to read a signal inside a subprogram if it is an interface element of the subprogram of mode `OUT'. For this reason, an intermediate temporary signal is created in the VHDL architecture.

The above points are further illustrated by the example below.

` System Tasks and Functions

There are no direct VHDL equivalents to Verilog system tasks or functions, so the translation is done by automatically creating equivalent procedures in the VHDL output file. Of all Verilog system tasks and functions, Verilog2VHDL supports those associated with formatted output, and $time and $fopen functions.

System Functions

$time function is translated into NOW function normalized by 1 ns (default) or by the timeunit specified with a `timescale directive.

Translation of $fopen("filename.ext") function results in a declaration of a file with the logical name "filename.ext". If $fopen function appears on the RHS of an assignment or as an argument to a task or a function, it is substituted by the channel descriptor number normally returned by a $fopen function call in Verilog (see assignment to file1 in the example below). As in Verilog, filechannel 1 is reserved for STDOUT ("/dev/tty" in VHDL). STDOUT channel is added automatically to the translation of a Verilog file with output system task calls.

System Tasks

The number of parameters of V2V_display is adjusted automatically to translate $(f)display or $(f)strobe call with the greatest number of parameters. Similarly, the number of parameters of V2V_write is adjusted automatically to translate the $(f)write call with the greatest number of parameters.

Verilog2VHDL Error Handling

Verilog2VHDL handles errors in the following way:

1. If a syntax error in encountered in the Verilog input file, the tool exits immediately after printing out the error message.

2. If an unsupported construct is encountered in the Verilog Input, a warning message is issued, and Verilog2VHDL continues processing.

3. If the unsupported construct is of the type `event', Verilog2VHDL exits after issuing appropriate error message.

Reserved words in Verilog2VHDL

It is important to note that VHDL is case-insensitive; and therefore `test' and `TEST' are the same. The user is advised not to use identifiers differing only in case in the Verilog file as this may result in incorrect VHDL.

Verilog2VHDL has a list of reserved words which are not allowed as identifiers in input Verilog code. When they appear in the input Verilog code, Verilog2VHDL creates legal VHDL names by modifying each reserved identifier to a VHDL extended identifier with the same name. For eg., VHDL reserved identifier `shared' would be modified to `\shared\'; all occurrences of `shared' will be changed to `\shared\'. Reserved identifiers follow below:

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Verilog vs VHDL: Explain by Examples

Last time , i presented in detail what actually fpga programming is and how to get started with fpga design. a brief history of verilog and vhdl was also discussed. if you search for the difference between verilog and vhdl, you will see many difference pages discussing this hdl language war, but most of them are short and not well-explained by examples for facilitating beginners or students' understanding., the difference between verilog and vhdl will be explained in detail by examples in this post. the advantages and disadvantages of verilog and vhdl will be also discussed..

Verilog vs VHDL: Explain by Example

HDL Modeling Capacity: Verilog vs VHDL

First of all, let's discuss hardware modeling capacities of verilog and vhdl since they are both hardware description languages for modeling hardware..

Verilog vs VHDL Modeling capacity

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verilog assign in vhdl

Verilog for VHDL (others => '0')?

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What is verilog syntax to do same? Thank you in advance

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Mark McDougall

> In VHDL, when we assign value to signal a, we can use following: > > // VHDL : assign all bits to zero > a <= (others => '0'); > > What is verilog syntax to do same?

-- Mark McDougall, Engineer Virtual Logic Pty Ltd, < > 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

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>Pasacco wrote: > >> In VHDL, when we assign value to signal a, we can use following: >> >> // VHDL : assign all bits to zero >> a <= (others => '0'); >> >> What is verilog syntax to do same? > >Ummm, a = 0; should work for vectors up to 32 bits, no?

Actually it's better than that. The bits of 'a' which are not assigned by '0' are filled with zeros so 'a=0' is guaranteed to initialize all bits of a to zero.

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> Pasacco wrote: > > > In VHDL, when we assign value to signal a, we can use following: > > > > // VHDL : assign all bits to zero > > a <= (others => '0'); > > > > What is verilog syntax to do same? > > Ummm, a = 0; should work for vectors up to 32 bits, no? >

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Assignment Symbol in VHDL

VHDL assignments are used to assign values from one object to another. In VHDL there are two assignment symbols:

Either of these assignment statements can be said out loud as the word “gets”. So for example in the assignment: test <= input_1; You could say out loud, “The signal test gets (assigned the value from) input_1.”

Note that there is an additional symbol used for component instantiations (=>) this is separate from an assignment.

Also note that <= is also a relational operator (less than or equal to). This is syntax dependent. If <= is used in any conditional statement (if, when, until) then it is a relational operator , otherwise it’s an assignment.

One other note about signal initialization: Signal initialization is allowed in most FPGA fabrics using the := VHDL assignment operator. It is good practice to assign all signals in an FPGA to a known-value when the FPGA is initialized. You should avoid using a reset signal to initialize your FPGA , instead use the := signal assignment.

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Find a training course, wire assignments.

A wire can be declared and continuously assigned in a single statement - a wire assignment. This is a shortcut which saves declaring and assigning a wire separately. There are no advantages or disadvantages between the two methods other than the obvious difference that wire assignments reduce the size of the text.

Later on we will discuss delays on assignments and wires. A delay in a wire assignment is equivalent to a delay in the corresponding continuous assignment, not a delay on the wire. Thus it could be necessary to separate the wire declaration from the continuous assignment to put the delay onto the wire rather than the assignment. Note that this is a subtle point that you are unlikely to encounter in practice!

Verilog: Using wire assignments to describe an AOI gate module

So in this sample code, each of the wire declarations and its corresponding assign statement are effectively merged into one wire assignment.

Note the use of a block comment in the Verilog code, rather than the line comments we have seen so far. A block comment may span several lines of code. Block comments may not be nested.

verilog assign in vhdl

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  1. Signal Assignment VHDL vs. Verilog

    Verilog is an alternative language to VHDL for specifying RTL for logic synthesis. • VHDL similar to Ada programming language in.

  2. Appendix B: Verilog2VHDL Translation Reference

    This is wholly equivalent to the concurrent signal assignment in VHDL with inertial delays. Example. Verilog. VHDL. `timescale 1ns/1ns.

  3. VHDL and Verilog

    Verilog uses an “assign” statement, and assigns outputs to combinational nets immediately;. • VHDL uses a signal assignment operator (<=), and requires that

  4. Verilog vs VHDL: Explain by Examples

    It means that there will be a compiler error if you mix data types or mismatch signals when assigning in VHDL. On the other hand, Verilog is a loosely typed

  5. The Verilog hardware description language

    //assign statement using the conditional operator (in lieu of always block).

  6. Verilog for VHDL (others => '0')?

    In VHDL, when we assign value to signal a, we can use following: // VHDL : assign all bits to zero a <= (others => '0');. What is verilog syntax to do same?

  7. Assignment Symbol

    One other note about signal initialization: Signal initialization is allowed in most FPGA fabrics using the := VHDL assignment operator. It is

  8. Variable and Signal Assignment in a Process Example (VHDL)

    Filename: variable_in_process.vhd -- Variable and signal assignment in a process -- variable_in_process.vhd -- library ieee; use ieee.std_logic_1164.all;

  9. A short introduction to Verilog for those who know VHDL

    assign button = x & ~y; //continuous assignment.

  10. A short introduction to Verilog for those who know VHDL

    Verilog vs VHDL. 95. 2001. VHDL ... assign button = x & ~y;.

  11. Wire Assignments

    So in this sample code, each of the wire declarations and its corresponding assign statement are effectively merged into one wire assignment. Note the use of a