blocking and non blocking assignment verilog

Verilog Blocking & Non-Blocking

Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.

Note that there are two initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variable b and c are 8'hxx in the first display statement. This is because variable b and c assignments have not been executed yet when the first $display is called.

In the next example, we'll add a few delays into the same set of statements to see how it behaves.

Non-blocking

Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment. If we take the first example from above, replace all = symobls with a non-blocking assignment operator , we'll see some difference in the output.

See that all the $display statements printed 'h'x . The reason for this behavior lies in the way non-blocking assignments are executed. The RHS of every non-blocking statement of a particular time-step is captured, and moves onto the next statement. The captured RHS value is assigned to the LHS variable only at the end of the time-step.

So, if we break down the execution flow of the above example we'll get something like what's shown below.

Next, let's use the second example and replace all blocking statements into non-blocking.

Once again we can see that the output is different than what we got before.

If we break down the execution flow we'll get something like what's shown below.

Blocking and Non-blocking Assignment in Verilog

• Assignment is only done in procedural block(always ot initial block)
• Both combintational and sequential circuit can be described.
• Assignment can only possible to reg type irrespect of circuit type

Let's say we want to describe a 4-bit shift register in Verilog. For this, we are required to declare a 3-bit reg type variable.

The output of shift[0] is the input of shift[1], output of shift[1] is input of shift[2], and all have the same clock. Let's complete the description using both assignment operator.

Non-Blocking Assignment

When we do synthesis, it consider non-blocking assignment separately for generating a netlist. If we see register assignment in below Verilog code, all register are different if we consider non-blocking assignment separately. If you do the synthesis, it will generate 3 registers with three input/output interconnects with a positive edge clock interconnect for all register. Based on the Verilog description, all are connected sequentially because shift[0] is assigned d, shift[1] is assigned shift[0], and shift[2] is assigned shift[1].

Blocking Assignment

If we use blocking assignment and do the syhtheis, the synthesis tool first generate netlist for first blocking assignment and then go for the next blocking assignment. If in next blocking assignment, if previous output of the register is assigned to next, it will generate only a wire of previously assigned register.

In below Verilog code, even though all looks three different assignment but synthesis tool generate netlist for first blocking assigment which is one register, working on positive edge of clock, input d and output shift[0]. Since blocking assignment is used, for next blocking assignment, only wire is generated which is connected to shift[0]. Same is for next statement a wire is generated which is connected to shift[0].

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Comments (1)

hey in blocking assignment do we get shift in data i dont think so . we get all values same and equal to d.

Please do not focus on the module name; focus on how the netlist is generated after the synthesis.

Blocking vs. Nonblocking in Verilog

The concept of Blocking vs. Nonblocking signal assignments is a unique one to hardware description languages. The main reason to use either Blocking or Nonblocking assignments is to generate either combinational or sequential logic. In software, all assignments work one at a time. So for example in the C code below:

The second line is only allowed to be executed once the first line is complete. Although you probably didn’t know it, this is an example of a blocking assignment. One assignment blocks the next from executing until it is done. In a hardware description language such as Verilog there is logic that can execute concurrently or at the same time as opposed to one-line-at-a-time and there needs to be a way to tell which logic is which.

<=     Nonblocking Assignment

=      Blocking Assignment

The always block in the Verilog code above uses the Nonblocking Assignment, which means that it will take 3 clock cycles for the value 1 to propagate from r_Test_1 to r_Test_3. Now consider this code:

See the difference? In the always block above, the Blocking Assignment is used. In this example, the value 1 will immediately propagate to r_Test_3 . The Blocking assignment immediately takes the value in the right-hand-side and assigns it to the left hand side. Here’s a good rule of thumb for Verilog:

In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking assignments. If you want to create combinational logic use an always block with Blocking assignments. Try not to mix the two in the same always block.

Nonblocking and Blocking Assignments can be mixed in the same always block. However you must be careful when doing this! It’s actually up to the synthesis tools to determine whether a blocking assignment within a clocked always block will infer a Flip-Flop or not. If it is possible that the signal will be read before being assigned, the tools will infer sequential logic. If not, then the tools will generate combinational logic. For this reason it’s best just to separate your combinational and sequential code as much as possible.

One last point: you should also understand the semantics of Verilog. When talking about Blocking and Nonblocking Assignments we are referring to Assignments that are exclusively used in Procedures (always, initial, task, function). You are only allowed to assign the reg data type in procedures. This is different from a Continuous Assignment . Continuous Assignments are everything that’s not a Procedure, and only allow for updating the wire data type.

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Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

There are Two types of Procedural Assignments in Verilog.

• Blocking Assignments
• Nonblocking Assignments

To learn more about Delay: Read  Delay in Assignment (#) in Verilog

Blocking assignments

• Blocking assignments (=) are done sequentially in the order the statements are written.
• A second assignment is not started until the preceding one is complete. i.e, it blocks all the further execution before it itself gets executed.

Non-Blocking assignments

• Nonblocking assignments (<=), which follow each other in the code, are started in parallel.
• The right hand side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none, the start of the procedure.
• The transfer to the left hand side is made according to the delays. An intra- assignment delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking. However normal delays are cumulative and will delay the output.
• Non-blocking schedules the value to be assigned to the variables but the assignment does not take place immediately. First the rest of the block is executed and the assignment is last operation that happens for that instant of time.

To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments

The following example shows  interactions  between blocking  and non-blocking for simulation only (not for synthesis).

For Synthesis (Points to Remember):

• One must not mix “<=” or “=” in the same procedure.
• “<=” best mimics what physical flip-flops do; use it for “always @ (posedge clk..) type procedures.
• “=” best corresponds to what c/c++ code would do; use it for combinational procedures.

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• Synthesis and Functioning of Blocking and Non-Blocking Assignments.
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• Module Instantiation in Verilog

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Verilog Blocking vs Non-Blocking Assignments

In writing verilog one of the common misunderstandings is the difference between a blocking and a non-blocking assignment. Explain the difference and the syntax used with these assignments?

There are synthesis differences between a blocking statement and a non-blocking statement.

Blocking Assignment

The syntax for a blocking assignment is:

always @ (pos edge clk) begin x=y; y=z; end

In this blocking assignment immediately after rising transition of the clk signal, x=y=z.

Non-Blocking Assignment

The syntax for a non-blocking assignment is:

always @ (pos edge clk) begin x<=y; y<=z; end

In this non-blocking assignment immediately after rising transition of the clk signal, x=y and y=z, but x!=z. Synthesis for this code would typically create a register for x and a register for y. Where blocking assignments often are synthesized as logic.

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Non Blocking Proceduaral assignments

The non-blocking assignment statement starts its execution by evaluating the RHS operand at the beginning of a time slot and schedules its update to the LHS operand at the end of a time slot. Other Verilog statements can be executed between the evaluation of the RHS operand and the update of the LHS operand. As it does not block other Verilog statement assignments, it is called a non-blocking assignment.

A less than or equal to ‘<=’ is used as a symbol for the non-blocking assignment operator.

• If <= symbol is used in an expression then it is interpreted as a relational operator. 
• If <= symbol is used in an assignment then it is interpreted as a non blocking operator. 

How race around condition is resolved in a nonblocking assignment?

If a variable is used in LHS of blocking assignment in one procedural block and the same variable is used in RHS of another blocking assignment in another procedural block.

In this example, 

Since procedural blocks (both initial and always) can be executed in any order.

In a non-blocking assignment statement no matter what is the order of execution, both RHS of the assignments (y <= data and data <= y) are evaluated at the beginning of the timeslot and LHS operands are updated at the end of a time slot. Thus, race around condition is avoided as there is no dependency on execution order and the order of execution of these two statements can be said to happen parallelly.

Verilog procedural assignment guidelines

For a beginner in Verilog, blocking and non-blocking assignments may create confusion. If are used blindly, it may create race conditions or incorrect synthesizable design. Hence, it is important to understand how to use them. To achieve synthesized RTL correctly, Verilog coding guidelines for blocking and non-blocking assignments are mentioned below

• Use non-blocking assignments for modeling flip flops, latches, and sequential logic.
• Use blocking assignment to implement combinational logic in always block.
• Use non-blocking assignment to implement sequential logic in always block.
• Do not mix blocking and non-blocking assignments in single always block i.e. For the implementation of sequential and combination logic in a single ‘always’ block, use non-blocking assignments.
• Do not assign value to the same variable in the different procedural blocks.
• Use non-blocking assignments while modeling both combination and sequential logic within the same always block.
• Avoid using #0 delay in the assignments.

Verilog Tutorials

[Verilog] 理解 Blocking non-Blocking assignments(一)

推荐Sutherland的PPT:

Verilog里有连续赋值(Continuous assignment) ，过程赋值（Procedural assignment)，还有过程连续赋值(Procedural Continuous assignment)。

过程赋值又有阻塞赋值和非阻塞赋值。

"=" 表示阻塞过程赋值（Blocking Procedural assignment）, "<="表示非阻塞过程赋值(Non-blocking Procedural assignment)。

过程赋值的过程可以理解为两个步骤：右式计算和左式赋值。

例如 a = a + 1，先计算"="右边的 a+1，然后将这个值赋给"="左边的a。

=，阻塞赋值，可以认为：

• 过程中的执行流被阻塞，直到赋值完成
• 在同一时间步上的并发语句的计算被阻塞，直到赋值完成

<=，非阻塞赋值，可以理解为：

• 左式赋值延迟到当前同一时间步的其它右式计算都完成以后进行
• 过程中的执行流继续进行，不被阻塞

• non-blocking assignment，RHS(right-hand side)计算在Q1，LHS(left-hand side)赋值在Q2
• blocking assignment，计算和赋值在Q1一步完成

3. 连续赋值也是在Q1计算与赋值一步完成

4. $display, $write 计算和打印输出在Q1完成

5. $strobe, $monitor计算和打印输出在Q3完成

这对上面的描述，看下面的例子：

在clk的上升沿，有4个语句：

• 阻塞赋值, blocking = a+1
• 非阻塞赋值, non_blocking <= a+1

这四个语句同时发生。在同一个时间步，发生的过程分析如下：

Q1（按语句先后顺序。见特别申明的变化。）

阻塞赋值一步完成。即：blocking=a+1，计算和赋值一步完成，blocking=2

非阻塞赋值，即：non_blocking<=a+1 的右式计算。a+1计算结果为2（但还未赋给左式！）

$display计算及打印输出，此时结果: blocking为2，non_blocking还保留初始值0

非阻塞赋值语句，给左式赋值，即：non_blocking=2

$strobe计算及打印输出，此时：blocking=2，non_blocking=2

所以，最终看到的运行输出是：

特别申明一下。在Q1里，存在一个竞争：变量blocking的阻塞赋值和$display。由于仿真软件的限制，仿真的结果是按照语句的先后顺序。 但理论上它们同时发生，不保证先后顺序。存在竞争的风险，意味着交换两条语句的前后顺序，会导致不同的结果。

$display在前，阻塞赋值在后，结果如下

但是，变量non_blocking的赋值和$display(或$strobe)不存在这样的竞争，因为$display在Q1，赋值在Q2，$strobe在Q3。交换非阻塞赋值和$display的顺序不影响结果。

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