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Verilog Delay Control

There are two types of timing controls in Verilog - delay and event expressions. The delay control is just a way of adding a delay between the time the simulator encounters the statement and when it actually executes it. The event expression allows the statement to be delayed until the occurrence of some simulation event which can be a change of value on a net or variable ( implicit event ) or an explicitly named event that is triggered in another procedure.

Simulation time can be advanced by one of the following methods.

Gates and nets that have been modeled to have internal delays also advance simulation time.

Delay Control

If the delay expression evaluates to an unknown or high-impedance value it will be interpreted as zero delay. If it evaluates to a negative value, it will be interpreted as a 2's complement unsigned integer of the same size as a time variable.

Note that the precision of timescale is in 1ps and hence $realtime is required to display the precision value for the statement with a delay expression (a+b)*10ps.

Event Control

Value changes on nets and variables can be used as a synchronization event to trigger execution other procedural statements and is an implicit event. The event can also be based on the direction of change like towards 0 which makes it a negedge and a change towards 1 makes it a posedge .

  • A negedge is when there is a transition from 1 to X, Z or 0 and from X or Z to 0
  • A posedge is when there is a transition from 0 to X, Z or 1 and from X or Z to 1

A transition from the same state to the same state is not considered as an edge. An edge event like posedge or negedge can be detected only on the LSB of a vector signal or variable. If an expression evaluates to the same result it cannot be considered as an event.

Named Events

The keyword event can be used to declare a named event which can be triggered explicitly. An event cannot hold any data, has no time duration and can be made to occur at any particular time. A named event is triggered by the -> operator by prefixing it before the named event handle. A named event can be waited upon by using the @ operator described above.

Named events can be used to synchronize two or more concurrently running processes. For example, the always block and the second initial block are synchronized by a_event . Events can be declared as arrays like in the case of b_event which is an array of size 5 and the index 3 is used for trigger and wait purpose.

Event or operator

The or operator can be used to wait on until any one of the listed events is triggered in an expression. The comma , can also be used instead of the or operator.

Implicit Event Expression List

The sensitivity list or the event expression list is often a common cause for a lot of functional errors in the RTL. This is because the user may forget to update the sensitivity list after introducing a new signal in the procedural block.

If the user decides to add new signal e and capture the inverse into z , special care must be taken to add e also into the sensitivity list.

Verilog now allows the sensitivity list to be replaced by * which is a convenient shorthand that eliminates these problems by adding all nets and variables that are read by the statemnt like shown below.

Level Sensitive Event Control

Execution of a procedural statement can also be delayed until a condition becomes true and can be accomplished with the wait keyword and is a level-sensitive control.

The wait statement shall evaluate a condition and if it is false, the procedural statements following it shall remain blocked until the condition becomes true.

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Digital Logic Design Using Verilog pp 343–365 Cite as

Non-synthesizable Verilog Constructs and Testbenches

  • Vaibbhav Taraate 2  
  • First Online: 01 November 2021

2060 Accesses

The chapter discusses about the inter-delay, intra-delay assignments and other non-synthesizable constructs useful during the testbenches. The chapter is useful to understand about the non-synthesizable constructs and how to check for the functional correctness of the design.

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Taraate, V. (2022). Non-synthesizable Verilog Constructs and Testbenches. In: Digital Logic Design Using Verilog. Springer, Singapore. https://doi.org/10.1007/978-981-16-3199-3_15

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Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

There are Two types of Procedural Assignments in Verilog.

  • Blocking Assignments
  • Nonblocking Assignments

To learn more about Delay: Read  Delay in Assignment (#) in Verilog

Blocking assignments

  • Blocking assignments (=) are done sequentially in the order the statements are written.
  • A second assignment is not started until the preceding one is complete. i.e, it blocks all the further execution before it itself gets executed.

Blocking

Non-Blocking assignments

  • Nonblocking assignments (<=), which follow each other in the code, are started in parallel.
  • The right hand side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none, the start of the procedure.
  • The transfer to the left hand side is made according to the delays. An intra- assignment delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking. However normal delays are cumulative and will delay the output.
  • Non-blocking schedules the value to be assigned to the variables but the assignment does not take place immediately. First the rest of the block is executed and the assignment is last operation that happens for that instant of time.

Non_Blocking

To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments

The following example shows  interactions  between blocking  and non-blocking for simulation only (not for synthesis).

Mixed

For Synthesis (Points to Remember):

  • One must not mix “<=” or “=” in the same procedure.
  • “<=” best mimics what physical flip-flops do; use it for “always @ (posedge clk..) type procedures.
  • “=” best corresponds to what c/c++ code would do; use it for combinational procedures.

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Related posts:

  • Synthesis and Functioning of Blocking and Non-Blocking Assignments.
  • Delay in Assignment (#) in Verilog
  • Ports in Verilog Module
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Inertial & transport delays

Inertial delay.

Inertial delay models are simulation delay models that filter pulses that are shorted than the propagation delay of Verilog gate primitives or continuous assignments ( assign #5 y = ~a; )

​ COMBINATIONAL LOGIC ONLY !!!

Inertial delays swallow glitches sequential logic implemented with procedure assignments DON'T follow the rule

continuous assignments

Procedure assignment - combinational logic, procedure assignment - sequential logic.

As shown above, sequential logic DON'T follow inertial delay

Transport delay

Transport delay models are simulation delay models that pass all pulses, including pulses that are shorter than the propagation delay of corresponding Verilog procedural assignments

Transport delays pass glitches, delayed in time Verilog can model RTL transport delays by adding explicit delays to the right-hand-side (RHS) of a nonblocking assignment

nonblocking assignment

Blocking assignment.

It seems that new event is discarded before previous event is realized.

Verilog Nonblocking Assignments With Delays, Myths & Mysteries

Correct Methods For Adding Delays To Verilog Behavioral Models

Article (20488135) Title: Selecting Different Delay Modes in GLS (RAK) URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009bdLyEAI

Article (20447759) Title: Gate Level Simulation (GLS): A Quick Guide for Beginners URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000005xEorEAE

  • Delays in Verilog

03 Sep 2023

In our introductory article we saw that Verilog is an HDL simulation language and the simulation happens in the timescale which is provided in the code. Also, there are special delay operators in Verilog which can be used to provide in the simulation. In this article we learn more about these delays and why it is needed. We will focus more on the deign side in this article.

Need for delays!

We have already discussed how delays are used in a testbench and hence, in this article we will discuss the use of delay in design part. In test bench, delays are used to synchronize signals, components or generate stimulus at a specific event.

But delays are also used in the design to simulate the path and gate delays seen in real-life circuit. If in simulation we do not consider these factors, it can lead to setup or hold violations in silicon rendering the chip useless.

We must understand here that delay operator used in design are just for simulation and it will not be synthesized in actual hardware. Thus, delay operators have no effect on final netlist.

Path delays

Path delay is delay between two nodes of a circuit. In silicon, gates, or flops (nodes) will be connected through wire. The scale of design is exceedingly small usually in nanometres or micrometres and there would be lot of parallel wires in the silicon. Due to this, lot of parasitic RCs are seen in silicon. This can lead to the delay in the signal.

In Verilog, this delay is represented by using the delay operator before assignment statement.

Ex - #30 a => b;

Gate delays

Gate delays are due to the intrinsic nature of transistor used to design gate. Transistor can have parasitic RCs present between the drain, source, and gate. This affects the switching time of transistor and the Toff (fall) and Ton (rise) time of the gates. Thus, there is some delay in propagation of output from the actual input time. This delay is also known as propagation delay.

In Verilog, this delay can be represented by using delay operator just after the assignment operator.

Ex – a => #30 b;

Gate-level simulation

Once the RTL is synthesized and netlist are created, all the logic gets replaced with actual nets and gates/flops. In this stage, it is crucial to have a delay-based simulation on netlist to verify that the design is working with expected delays.

Gate delays are derived from the cell library used for synthesis. All cell libraries have a functional model which has gate delays defined for different gates.

Path delays are derived from the PnR (place and route) stage of the design cycle. In this stage, the cells are placed and specialized tool is used to extract RC details from the nets.

Setup and Hold Violation

Setup and hold violation are usually captured in STA (Static timing analysis) of the design cycle. But the delay-based simulation is also used to verify for any violation. This is known as dynamic timing analysis because there is input stimulus to the circuit which will change in the simulation. Let us understand these violations and what affect it have on the chip.

Setup Violation

Setup violation happens when the data path is slower than the clock path. Data path usually have a lot of gates in the path which can cause the overall delay in data path to be more than clock path. When this happens, clock will arrive earlier in a flop and flop will capture wrong data as data will take some more time to arrive.

If this violation is not captured in the design phase, then in silicon we need to decrease the clock speed to remove these violations. Reducing clock speed decreases the chip performance and thus not an ideal situation.

Some fixes for setup violation

  • Reduce buffers in the data path as this slows down the data path.
  • Relace a buffer with two inverters. Inverters have less than half of the delay of buffers.
  • Use repeaters in longer route to reduce parasitic RCs. There are lot more ways to fix setup violation which are out of scope of this article.

Hold Violation

Hold violation happens when data path is faster than the clock path. This means that the data will not be stable when flip flop samples the data and thus hold violation will happen.

If this violation is not captured in the design phase, then there is no way to remove these violations in chip and chip is useless. In simple terms ‘JUST DUMP THE CHIP’ .

Some fixes for hold violation.

Hold violations are easy to fix in design phase.

  • Add buffer in data path to increase delay.
  • Decrease cell size which will decrease drive load of the cell, ultimately increasing delay. Thus, we see that it is very crucial to identify these violations in design phase and use appropriate measures to solve them in design phase itself.

Setup and hold violation can be solved in numerous ways in the design phase. Having detailed discussion on the solutions is out of the scope of this article. Some of the solutions are mentioned above in respective violation section.

In this article, we saw how the delay-based simulation crucial role in identifying violations which can render the chip useless. Though delay operator does not play a direct role in the RTL design but is important in terms of simulation.

  • Introduction to Verilog
  • Verilog Event Semantics
  • Basics of Verilog
  • Verilog Syntax
  • Data Types in Verilog
  • Verilog Vectors
  • Verilog Arrays
  • Verilog Modules
  • Verilog Ports
  • Verilog Operators
  • Verilog Procedural Blocks
  • Verilog Assignments
  • Different types of loops in Verilog
  • Conditional Statements in Verilog
  • Verilog functions and tasks
  • Compiler Directives in Verilog
  • Verilog System Functions

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COMMENTS

  1. Verilog Inter and Intra Assignment Delay

    An intra-assignment delay is one where there is a delay on the RHS of the assignment operator. This indicates that the statement is evaluated and values of all signals on the RHS is captured first. Then it is assigned to the resultant signal only after the delay expires. module tb;

  2. Delay in Assignment (#) in Verilog

    Syntax: #delay. It delays execution for a specific amount of time, 'delay'. There are two types of delay assignments in Verilog: Delayed assignment:. #Δt variable = expression; // "expression" gets evaluated after the time delay Δt and assigned to the "variable" immediately Intra-assignment delay:

  3. Basic question on intra-assignment delay in Verilog

    Intra-assignment delays in a Verilog always block should NEVER be used (NEVER!). There is no known hardware that behaves like this intra-assignment delay using blocking assignments. If I could take this out of the Verilog language I would, but I can't because of backward compatibility. In Verilog training, I always say, "if your mother and I ...

  4. #20 Inter and intra assignment delay

    In this verilog tutorial use of inter assignment delay and intra assignment delay has been covered in details with verilog code. Most of the time during VLSI...

  5. Intra-assignment delay in verilog

    The a is assigned to x at simulation time 5, while b is assigned to y at simulation time 10. Now consider nonblocking assignment statements with intra-assignment delays that follow in a sequential block: initial begin. x<=#5 a; y<=#5 b; end. In the above case both a and b are concurrently assigned to x and y at simulation time 5.

  6. Verilog Inter and Intra Delay

    An inter-assignment delay statement has delay value on the left-hand side of the assignment operator. Inter assignment are those delay statements where the execution of the entire statement or assignment got delayed. In Verilog, Inter assignment delays often correspond to the inertial delay or the VHDL 's regular delay statements.

  7. verilog

    They produce different output when in toggles before the #5 delay is up. The non-blocking assignment will always delay in by #5 regardless of how fast in toggles. Examples on EDA Playground. Note the difference in sim output. Blocking assignment; Non-Blocking assignment

  8. PDF Correct Methods For Adding Delays To Verilog Behavioral Models

    Adding delays to the left hand side (LHS) of any sequence of blocking assignments to model combinational logic is also flawed. The adder_t7a example shown in Figure 4 places the delay on the first blocking assignment and no delay on the second assignment. This will have the same flawed behavior as the adder_t1 example.

  9. Verilog Delay Control

    Verilog Delay Control. There are two types of timing controls in Verilog - delay and event expressions. The delay control is just a way of adding a delay between the time the simulator encounters the statement and when it actually executes it. The event expression allows the statement to be delayed until the occurrence of some simulation event ...

  10. PDF Non-synthesizable Verilog Constructs and Testbenches

    Following are few of the important points to conclude the chapter. To verify the RTL design functionality, the testbench need to be coded using the non-synthesizable Verilog constructs. Testbench is driver to drive the stimulus to design under test. During the simulation, we can use inter- or intra-delay assignments.

  11. Verilog

    Table 7 Differences beetwen delays and intra-assignment timing control. A delay with an assignment works differently. An assignment will be delayed and then the current value of expression will be assigned. The repeat expression specifies how many occurrences of an event should appear before the assignment takes place (Example 3).

  12. Non-synthesizable Verilog Constructs and Testbenches

    To verify the RTL design functionality, the testbench need to be coded using the non-synthesizable Verilog constructs. 2. Testbench is driver to drive the stimulus to design under test. 3. During the simulation, we can use inter- or intra-delay assignments.

  13. Verilog inter vs intra delay

    It is not an intra-assignment delay. Time must advance by 5 for each loop of the always. The non-blocking assignment (NBA) is superfluous. Use a blocking assignment. always #5 clk = !clk; always clk = #5 !clk; // this is intra-assigment (blocking) delay. I have a fundamental verilog event region question that I want clarification on. The ...

  14. Timing Control

    Intra-assignment delays are analogous to utilising inter-assignment delays in conjunction with a temporary variable to hold the current value of a right-hand-side expression. Zero delay control. ... Verilog also supports level-sensitive timing control, which allows you to wait for a condition to be true before executing a statement or a block ...

  15. Delay after and before assignment in SV

    The intra-assignment delay statement is left over from very early Verilog before non-blocking assignments were added to the language. They no longer should be used. Basically. A = #delay B; is equivalent to. begin temp = B; #delay A = temp; end You ahould instead use A <= Delay B;

  16. Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

    An intra- assignment delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking. However normal delays are cumulative and will delay the output. Non-blocking schedules the value to be assigned to the variables but the assignment does not take place immediately.

  17. Inertial & transport delays

    Transport delay models are simulation delay models that pass all pulses, including pulses that are shorter than the propagation delay of corresponding Verilog procedural assignments. Transport delays pass glitches, delayed in time. Verilog can model RTL transport delays by adding explicit delays to the right-hand-side (RHS) of a nonblocking ...

  18. Delays in Verilog

    In Verilog, this delay can be represented by using delay operator just after the assignment operator. Ex - a => #30 b; Gate-level simulation. Once the RTL is synthesized and netlist are created, all the logic gets replaced with actual nets and gates/flops. In this stage, it is crucial to have a delay-based simulation on netlist to verify that ...

  19. How does #delay work for Verilog non-blocking statements?

    difference between blocking and non blocking statements with intra-assignment delay. 0. Why put delays in Verilog even for some simple assignment? 2. ... Verilog wait function explanation. 2. Why don't delays synthesize in Verilog? 0. verilog intra delay for both blocking and non-blocking statement. 0. Confusion regarding Delay inside an always ...

  20. verilog

    Viewed 920 times. 2. I am now confused by one piece of Verilog Code, its kind of testing the blocking or non-blocking assignment features that combination with Delay model. The code is below EDA Playground: module cl_tb; reg x,y,z; initial begin. x = 2; #4;